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19-2964; Rev 0; 8/03
KIT ATION EVALU BLE AVAILA
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
General Description Features
o Wide Input Voltage Range, 11V to 76V o Voltage Mode with Input Voltage Feed-Forward o Ripple-Phased Parallel Topology for High Current/Power Output o 2A Integrated High- and Low-Side MOSFET Drivers o SYNCIN And SYNCOUT Pins Enable 180 Out-OfPhase Operation o Programmable Brownout and Bootstrap UVLOs o High-Side Driver Bootstrap Capacitor Precharge Driver o Low Current-Limit Threshold for High Efficiency o Programmable Switching Frequency o Reference Voltage Soft-Start for Startup Without Overshoots o Startup Synchronization with Multiple Paralleled Primaries o Programmable Integrating Current-Limit Fault Protection o Look-Ahead PWM Signal for Secondary-Side Synchronous Rectifier Drivers o Look-Ahead Drivers for Either A High-Speed Optocoupler or Pulse Transformer o Wide -40C to +125C Operating Range o Thermally Enhanced 28-Pin TSSOP Package
MAX5051
The MAX5051 is a clamped, two-switch power-supply controller IC. This device can be used both in forward or flyback configurations with input voltage ranges from 11V to 76V. It provides comprehensive protection mechanisms against possible faults, resulting in very high reliability power supplies. When used in conjunction with secondary-side synchronous rectification, power-supply efficiencies can easily reach 92% for a +3.3V output power supply operated from a 48V bus. The integrated high- and low-side gate drivers provide more than 2A of peak gate-drive current to two external N-channel MOSFETs. Low startup current reduces the power loss across the bootstrap resistor. A feed-forward voltagemode topology provides excellent line rejection while avoiding the pitfalls of traditional current-mode control. The MAX5051 power-supply controller is primary as well as secondary-side parallelable, allowing the design of scaleable power systems when necessary. When paralleling the primary side, dedicated pins allow for simultaneous wakeup or shutdown of all paralleled units, thus preventing current-hogging during startup or fault conditions. The MAX5051 generates a lookahead signal for driving secondary-side synchronous MOSFETs. Special primary-side synchronization inputs/outputs allow two primaries to be operated 180 out of phase for increased output power and lower input ripple currents. The MAX5051 is available in a 28-pin TSSOP-EP package and operates over a wide -40C to +125C temperature range. Warning: The MAX5051 is designed to work with high voltages. Exercise caution.
Applications
High-Efficiency, Isolated Telecom/Datacom Power Supplies 48V and 12V Server Power Supplies 48V Power-Supply Modules 42V Automotive Power Systems Industrial Power Supplies
PART MAX5051AUI
Ordering Information
TEMP RANGE -40C to +125C PIN-PACKAGE 28-TSSOP-EP*
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
ABSOLUTE MAXIMUM RATINGS
AVIN, PVIN, XFRMRH to GND................................-0.3V to +80V BST to GND ............................................................-0.3V to +95V BST, DRVH to XFRMRH..........................................-0.3V to +12V REG9, DRVDD, DRVL to GND................................-0.3V to +12V DRVB, LXVDD, LXL, LXH to GND ..........................-0.3V to +12V UVLO, STT, COMP, CON to GND ..........................-0.3V to +12V FLTINT, RCFF to GND ............................................-0.3V to +12V REG5, CS, CSS, FB to GND .....................................-0.3V to +6V STARTUP, SYNCIN to GND......................................-0.3V to +6V SYNCOUT, RCOSC to GND .....................................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V LXL, LXH Current Continuous...........................................50mA DRVL, DRVH Current Continuous...................................100mA DRVL, DRVH Peak Current (<500ns) ....................................5A PVIN, REG9 Continuous Current ....................................+120mA REG5 Continuous Current ................................................+80mA DRVB, RCFF, RCOSC, CSS Continuous Current .............20mA COMP, SYNCOUT Continuous Current ............................20mA REG9, REG5, and COMP Short to GND ....................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (derate 23.8mW/C above +70C) .....1905mW 28-Pin TSSOP (JA)......................................................42C/W Operating Temperature Range .........................-40C to +125C Maximum Junction Temperature (TJ) ..............................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24k, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7F, CREG5 = 4.7F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. All driver, voltage-regulator, and reference outputs unconnected except for bypass capacitors.)
PARAMETER SUPPLY CURRENT (AVIN, PVIN) AVIN Standby Current PVIN Standby Current AVIN Supply Current PVIN Supply Current AVIN Input Voltage Range +9V LDO (REG9) PVIN Input Voltage Range REG9 Output-Voltage Set Point REG9 Line Regulation REG9 Load Regulation REG9 Dropout Voltage REG9 Undervoltage Lockout Threshold REG9 Undervoltage Lockout Threshold Hysteresis +5V LDO (REG5) REG5 Output-Voltage Set Point REG5 Load Regulation REG5 Dropout Voltage VREG5 IREG5 = 0 to 40mA IREG5 = 40mA, measured with respect to VREG9 0.5 4.8 5.1 50 V mV V VPVIN VREG9 Inferred from PVIN supply current test VPVIN = 11V VPVIN = 11V to 76V IREG9 = 0 to 80mA IREG9 = 80mA VREG9 falling 5.7 750 0.5 6.7 11 8.3 0.1 250 76 9.0 V V mV/V mV V V mV IASTBY IPSTBY IAVIN IPVIN VAVIN = VPVIN = 11V to 76V; VSTARTUP = VCS = 0V; VBST = VXFRMRH = VDRVDD = VREG9; RCFF floating VAVIN = VPVIN = 11V to 76V; VCS = 0V; VBST = VDRVDD = VREG9; VXFRMRH = 0V; STARTUP, RCFF floating Inferred from AVIN supply current test 11 300 400 0.65 8 450 650 1 12 76 A A mA mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
ELECTRICAL CHARACTERISTICS (continued)
(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24k, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7F, CREG5 = 4.7F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. All driver, voltage-regulator, and reference outputs unconnected except for bypass capacitors.)
PARAMETER SOFT-START/REFERENCE (CSS) Reference Voltage Soft-Start Pullup Current FB Input Range FB Input Current COMP Output Range COMP Output Sink Current COMP Output Source Current Open-Loop Gain Unity-Gain Bandwidth FB Offset Voltage COMP Output Slew Rate PVIN Undervoltage Lockout STT Threshold STT Input Impedance FLTINT Source Current FLTINT Shutdown Threshold FLTINT Restart Hysteresis PWM Period Maximum PWM Duty Cycle Maximum RCOSC Frequency Maximum SYNCIN Frequency SYNCIN High-Level Voltage SYNCIN Low-Level Voltage SYNCIN Pulldown Resistor SYNCIN Rising to SYNCOUT Falling Delay SYNCIN Falling to SYNCOUT Rising Delay VSTT RSTT IFLTINT VFLTINTSD VFLTINTHY tS DMAX fRCOSCMAX fSYNCIN VHSYNCIN VLSYNCIN 50% duty cycle Pulse rising Pulse falling 100 30 70 2.1 0.8 RRCOSC = 24k, CRCOSC = 100pF RRCOSC = 24k, CRCOSC = 100pF VFLTINT = 0V VFLTINT = rising GA BW VOS SR VCSS ICSS VFB IFB Inferred from FB offset voltage test VFB = VREF Inferred from FB offset voltage test VFB = 3V VFB = 0V 2.1V < VCOMP < 6V CCOMP = 50pF, ICOMP = 5mA VFB = 0 to 3V; VCOMP = 2.1V to 6V; ICOMP = -5mA to +5mA CCOMP = 50pF VPVIN rising VSTT rising 22 1.18 -3 1 23.5 1.24 100 90 2.9 0.9 3.9 48 1 500 25 1.30 2.1 20 30 80 3 +3 0 1.215 1.235 70 3 250 6.0 1.255 V A V nA V mA mA dB MHz mV V/s V V k A V V s % MHz kHz V V k ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5051
ERROR AMPLIFIER (CSS, FB, COMP)
PVIN UNDERVOLTAGE LOCKOUT (STT)
INTEGRATING FAULT PROTECTION (FLTINT)
OSCILLATOR (RCOSC, SYNCIN, SYNCOUT)
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
ELECTRICAL CHARACTERISTICS (continued)
(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24k, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7F, CREG5 = 4.7F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. All driver, voltage-regulator, and reference outputs unconnected except for bypass capacitors.)
PARAMETER SYNCOUT Voltage High SYNCOUT Voltage Low RCOSC Peak Trip Level RCOSC Valley Trip Level RCOSC Input Bias Current RCOSC Discharge MOSFET RDS(ON) RCOSC Discharge Pulse Width UNDERVOLTAGE LOCKOUT (UVLO) UVLO Threshold UVLO Hysteresis UVLO Input Bias Current PWM COMPARATOR RCFF Input Voltage Range Feed-Forward Discharge MOSFET RDS(ON) CON Input Voltage Range RCFF Level-Shift Voltage CON Input Bias Current Propagation Delay to Output VCPWM ICON tdCPWM DRVH, DRVL = unconnected, overdrive = 50mV, measured from CON to DRVL LXH sourcing 10mA, VLXVDD = VREG5 LXL sinking 10mA, VLXVDD = VREG5 3 2.0 RDS(RCFF) Sinking 10mA 0 2.2 -2 90 0 50 3 100 6 2.4 +2 V V V A ns VUVLO VHYS IBUVLO VUVLO = 2.5V -100 VUVLO rising 1.18 1.24 130 +100 1.30 V mV nA Sinking 10mA VTH SYMBOL Sinking 2.4mA 2.5 0.2 -0.3 50 50 100 CONDITIONS Sourcing 1.2mA MIN 4.5 TYP MAX 5.1 0.3 UNITS V V V V A ns
SYNCHRONOUS RECTIFIER PULSE TRANSFORMER DRIVER (LXVDD, LXH, LXL) High-Side MOSFET RDS(ON) Low-Side MOSFET RDS(ON) LXH Rising to DRVL Rising Delay CURRENT-LIMIT COMPARATOR (CS) Current-Limit Threshold Voltage Current-Limit Input Bias Current Propagation Delay to Output VILIM IBILIM tdILIM 0 < VCS < 0.3V DRVH, DRVL = unconnected, overdrive = 10mV, measured from CS to DRVL 144 -2 100 154 164 +2 mV A ns RDSLXH RDSLXL 6.5 5 90 12 10 ns
LOW-SIDE MOSFET DRIVER (DRVDD, DRVL, PGND) Peak Source Current Peak Sink Current DRVL Resistance Sourcing DRVL Resistance Sinking VDRVL = 0V, pulse width < 100ns; VDRVDD = VREG9 VDRVL = VREG9, pulse width < 100ns; VDRVDD = VREG9 IDRVL = 50mA, VDRVDD = VREG9 IDRVL = -50mA, VDRVDD = VREG9 2 5 1.7 0.6 3.5 1.4 A A
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
ELECTRICAL CHARACTERISTICS (continued)
(AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24k, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7F, CREG5 = 4.7F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. All driver, voltage-regulator, and reference outputs unconnected except for bypass capacitors.)
PARAMETER SYMBOL CONDITIONS VDRVH = GND, pulse width < 100ns, VBST = VREG9, VXFRMRH = 0V VDRVH = VBST, pulse width < 100ns, VBST = VREG9, VXFRMRH = 0V IDRVH = 50mA, VBST = VREG9, VXFRMRH = 0V IDRVH = -50mA, VBST = VREG9, VXFRMRH = 0V MIN TYP MAX UNITS
MAX5051
HIGH-SIDE MOSFET DRIVER (BST, DRVH, XFRMRH) Peak Source Current Peak Sink Current DRVH Resistance Sourcing DRVH Resistance Sinking Skew Between Low-Side and High-Side Drivers BOOST CAPACITOR CHARGE MOSFET (DRVB) DRVB Resistance Sourcing DRVB Resistance Sinking Delay from Clock Fall One-Shot Pulse Width STARTUP (STARTUP) Startup Threshold Startup Threshold Hysteresis Internal Pullup Current STARTUP Pulldown MOSFET RDS(ON) OVERTEMPERATURE SHUTDOWN Shutdown Junction Temperature Hysteresis Temperature rising 150 10 C C ISTARTUP Sinking 10mA VSTARTUP VSTARTUP rising 1.4 330 50 50 100 2.1 V mV A IDRVB = 50mA IDRVB = 50mA 8 5 200 300 35 35 ns ns 2 5 1.7 0.6 0 3.5 1.4 A A ns
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
Typical Operating Characteristics
(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24k, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7F, CREG5 = 4.7F, TA = +25C, unless otherwise noted.)
AVIN STANDBY CURRENT vs. AVIN SUPPLY VOLTAGE
MAX5051 toc01
AVIN STANDBY CURRENT vs. TEMPERATURE
MAX5051 toc02
PVIN STANDBY CURRENT vs. SUPPLY VOLTAGE
VUVLO = 0V
MAX5051 toc03
300 290 AVIN STANDBY CURRENT (A) 280 270 260 250 240 230 220 210 200 10
280 270 AVIN STANDBY CURRENT (A) 260 250 240 230 220 210 200 190 180
VUVLO = 0V
VUVLO = 0V
600 500 400 300 200 100 0
20
30
40
50
60
70
80
-50
-25
0
25
50
75
100
125
PVIN STANDBY CURRENT (A)
10
20
30
40
50
60
70
80
AVIN SUPPLY VOLTAGE (V)
TEMPERATURE (C)
PVIN SUPPLY VOLTAGE (V)
PVIN STANDBY CURRENT vs. TEMPERATURE
MAX5051 toc04
PVIN STARTUP VOLTAGE vs. TEMPERATURE
MAX5051 toc05
REG9 OUTPUT VOLTAGE vs. PVIN VOLTAGE
MAX5051 toc06
600 500 400 300 200 100 0
VUVLO = 0V
23.6 STT = FLOATING PVIN STARTUP VOLTAGE (V) 23.5 23.4 23.3 23.2 23.1 23.0
8.805
PVIN STANDBY CURRENT (A)
REG9 OUTPUT VOLTAGE (V)
8.802
8.799
8.796
8.793
8.970 -50 -25 0 25 50 75 100 125 10 20 30 40 50 60 70 80 TEMPERATURE (C) PVIN VOLTAGE (V)
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
REG9 OUTPUT VOLTAGE vs. TEMPERATURE
MAX5051 toc07
REG9 OUTPUT VOLTAGE vs. REG9 OUTPUT CURRENT
8.9 REG9 OUTPUT VOLTAGE (V) 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8.0 4.0 0 20 40 60 80 100 120 140 160 0 10
MAX5051 toc08
REG5 OUTPUT VOLTAGE vs. REG5 OUTPUT CURRENT
MAX5051 toc09
8.90 8.88 REG9 OUTPUT VOLTAGE (V) 8.86 8.84 8.82 8.80 8.78 8.76 8.74 8.72 8.70 -50 -25 0 25 50 75 100
9.0
6.0
REG5 OUTPUT VOLTAGE (V)
5.6
5.2
4.8
4.4
125
20
30
40
50
60
70
80
90
TEMPERATURE (C)
REG9 OUTPUT CURRENT (mA)
REG5 OUTPUT CURRENT (mA)
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
Typical Operating Characteristics (continued)
(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24k, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7F, CREG5 = 4.7F, TA = +25C, unless otherwise noted.)
REG5 OUTPUT VOLTAGE vs. TEMPERATURE
MAX5051 toc10
MAX5051
AVIN SUPPLY CURRENT vs. TEMPERATURE
MAX5051 toc11
PVIN SUPPLY CURRENT vs. TEMPERATURE
VPVIN = 12V
MAX5051 toc12
5.001 5.000 4.999 OUTPUT VOLTAGE (V) 4.998 4.997 4.996 4.995 4.994 4.993 4.992 4.991 4.990 -50 -25 0 25 50 75 100
700 600 AVIN SUPPLY CURRENT (A) 500 400 300 200 100 0
7.2 7.1 7.0 6.9 6.8 6.7 6.6
VUVLO = 0V
125
PVIN SUPPLY CURRENT (mA)
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
SOFT-START/REFERENCE VOLTAGE vs. TEMPERATURE
MAX5051 toc13
CSS SOFT-START CURRENT vs. TEMPERATURE
MAX5051 toc14
UVLO THRESHOLD vs. TEMPERATURE
1.235 1.230
MAX5051 toc15
1.245 SOFT-START/REFERENCE VOLTAGE (V) 1.240 1.235 1.230 1.225 1.220 1.215 1.210 1.205 1.200 -50 -25 0 25 50 75 100
90 CSS SOFT-START CURRENT (A) 85 80 75 70 65
1.240
UVLO (V) -50 -25 0 25 50 75 100 125
1.225 1.220 1.215 1.210 1.205
60 125 TEMPERATURE (C) TEMPERATURE (C)
1.200 -50 -25 0 25 50 75 100 125 TEMPERATURE (C)
STT STARTUP THRESHOLD vs. TEMPERATURE
MAX5051 toc16
FLTINT CURRENT vs. TEMPERATURE
MAX5051 toc17
RCFF LEVEL-SHIFT VOLTAGE vs. TEMPERATURE
2.29 RCFF LEVEL-SHIFT VOLTAGE (V) 2.28 2.27 2.26 2.25 2.24 2.23 2.22 2.21 2.20
MAX5051 toc18
1.240 1.235 1.230 1.225 STT (V) 1.220 1.215 1.210 1.205 1.200 -50 -25 0 25 50 75 100
95 94 93 FLTINT CURRENT (A) 92 91 90 89 88 87 86 85
2.30
125
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
Typical Operating Characteristics (continued)
(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24k, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7F, CREG5 = 4.7F, TA = +25C, unless otherwise noted.)
CURRENT-LIMIT THRESHOLD vs. TEMPERATURE
MAX5051 toc19
OPEN-LOOP GAIN/PHASE vs. FREQUENCY
100 80 60 GAIN (dB) 40 20 PHASE 0 -20 0.01
MAX5051 toc20
COMP OUTPUT VOLTAGE vs. TEMPERATURE
240 210 PHASE (DEGREES) 180 150 120 90 60 30 COMP OUTPUT VOLTAGE (V) 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) ISINK = 5mA ISOURCE = 5mA
MAX5051 toc21
170 CS THRESHOLD VOLTAGE (mV) 165 160 155 150 145 140 -50 -25 0 25 50 75 100
270
8
GAIN
125
0.1
1
10
100
0 1000 10,000
TEMPERATURE (C)
FREQUENCY (kHz)
DRVH AND DRVL RDSON vs. TEMPERATURE
MAX5051 toc22
LXL AND LXH RDSON vs. TEMPERATURE
MAX5051 toc23
SWITCHING PERIOD vs. RRCOSC
45 40 SWITCHING PERIOD (s) 35 30 25 20 15 10 5 0
MAX5051 toc24
4.0 3.5 3.0 RDSON ()
12 11 10
50
RDSON ()
2.5 2.0 1.5 1.0 0.5 0 -50
DRVH AND DRVL SOURCING 50mA
9 LXH SOURCING 10mA 8 7 6 LXH SINKING 10mA
DRVH AND DRVL SINKING 50mA -25 0 25 50 75 100 125
5 4 -40 -15 10 35 60 85 110
0
40
80
120
160
200
TEMPERATURE (C)
TEMPERATURE (C)
RRCOSC (k)
NORMALIZED SWITCHING FREQUENCY vs. TEMPERATURE
MAX5051 toc25
SYNCIN TO SYNCOUT PROPAGATION DELAY vs. TEMPERATURE
MAX5051 toc26
DRVH MAXIMUM DUTY CYCLE vs. TEMPERATURE
49.6 49.2 DRVH DUTY CYCLE (%) 48.8 48.4 48.0 47.6 47.2 46.8 46.4 46.0
MAX5051 toc27
1.020 NORMALIZED SWITCHING FREQUENCY 1.010 1.000 0.990 0.980 0.970 0.960 SWITCHING 0.950 -50 -25 0 25 50 75 100
130 120 PROPAGATION DELAY (ns) 110 100 90 80 70 60 50 40 30 SYNCIN RISE TO SYNCOUT FALL SYNCIN FALL TO SYNCOUT RISE
50.0
125
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
Typical Operating Characteristics (continued)
(VAVIN = VPVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24k, CCSS = 10nF, CRCOSC = 100pF, CREG9 = 4.7F, CREG5 = 4.7F, TA = +25C, unless otherwise noted.)
CON TO DRVL PROPAGATION DELAY vs. TEMPERATURE
105 PROPAGATION DELAY (ns) 100 95 90 85 80 75 70 65 60 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) 50mV OVERDRIVE
MAX5051 toc28
MAX5051
CS CURRENT LIMIT TO DRVH PROPAGATION DELAY vs. TEMPERATURE
50mV OVERDRIVE 140 PROPAGATION DELAY (ns) 130 120 110 100 90 80 -50 -25 0 25 50 75 100 125 TEMPERATURE (C)
MAX5051 toc29
110
150
Pin Description
PIN 1 2 3 4 5 6 7 8 9 NAME RCOSC SYNCOUT RCFF CON CSS COMP FB REG5 REG9 FUNCTION Oscillator Frequency Set Input. Connect a resistor from RCOSC to REG5 and a capacitor from RCOSC to GND to set the oscillator frequency. Switching frequency is 1/2 the frequency of the sawtooth signal at RCOSC. Synchronization Output. Synchronization signal to drive SYNCIN of a second MAX5051, if used. Feed-Forward Input. Connect a resistor from RCFF to AVIN and a capacitor from RCFF to GND. This is the PWM ramp. PWM Comparator Noninverting Input. Connect CON to the optocoupler output for isolated applications, or to COMP for nonisolated applications. Soft-Start and Reference. Connect a 0.01F or greater capacitor from CSS to GND. The 1.24V reference voltage appears across this capacitor. Internal Error Amplifier Output Feedback Input. Inverting input of the internal error amplifier. The soft-started reference is connected to the noninverting input of this amplifier. 5V Linear Regulator Output. Bypass REG5 to GND with a 4.7F ceramic capacitor. 9V Linear Regulator Output. Bypass REG9 to GND with a 4.7F ceramic capacitor. Regulator Voltage Input. Voltage input to the internal 5V and 9V linear regulators. A high-value resistor connected from the input supply to PVIN provides the necessary current to charge up the startup capacitor, and the 400A standby current required by the MAX5051. After startup, the output of a tertiary winding is used to provide continued bias to the controller. Startup Threshold Input. Leave STT floating for a default startup voltage of 24V at PVIN. STT can be modified by connecting external resistors. For high accuracy, choose external resistors with 50k or less impedance looking back into the divider. Supply Input for the Secondary-Side Synchronous Pulse Transformer or Optocoupler Driver. LXVDD is normally connected to REG5.
10
PVIN
11
STT
12
LXVDD
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
Pin Description (continued)
PIN 13 NAME LXH FUNCTION Synchronous-Pulse Transformer Driver, PMOS Open Drain. LXH is the high-side driver for the secondaryside synchronous-pulse transformer. LXH can also drive a high-speed switching optocoupler. If not used, connect LXH to LXVDD. Synchronous-Pulse Transformer Driver, NMOS Open Drain. LXL is the low-side driver for the secondaryside synchronous-pulse transformer. LXL can also drive a high-speed switching optocoupler. If not used, connect LXL to PGND. Current-Sense Input. The current-limit threshold is internally set to 156mV relative to PGND. The device has an internal noise filter. If necessary, connect an additional external RC filter. Gate-Drive Output for Low-Side MOSFET. DRVL is capable of sourcing and sinking approximately 2A peak current. Power Ground Supply Input for Low-Side MOSFET Driver. Bypass DRVDD locally with good quality 1F || 0.1F ceramic capacitors. DRVDD is normally connected to REG9. Gate-Drive Output for Boost MOSFET. Connect the gate of a small high-voltage external FET to this pin to enable charging of the high-side boost capacitor connected between pins 20 and 22. This FET may be necessary to keep the boost capacitor charged at light loads. Transformer Input. Transformer primary high-side connection. Gate-Drive Output for High-Side MOSFET Boost Input. Boost supply connection point for the high-side MOSFET driver. Connect at least a 1F || 0.1F ceramic capacitor from BST to XFRMRH with short and wide PC board traces. If the voltage across the boost capacitor falls below the high-side undervoltage lockout threshold, the DRVH output stops switching. Supply Voltage Input. Connect AVIN directly to the input supply line. Analog Signal Ground Undervoltage Lockout Input. An external voltage-divider from the input supply sets the startup voltage; the threshold is 1.24V with 130mV hysteresis. UVLO can also be used as a shutdown input. If unused, connect UVLO to REG5 Startup Input. STARTUP coordinates simultaneous startup of multiple units from faults, during initial turnon, and UVLO recovery. When paralleling the secondaries of two MAX5051's, the STARTUP inputs of each device must be connected together. Fault Integration Input. During persistent current-limit faults, a capacitor connected to FLTINT is charged with an internal 90A current source. Switching is terminated when the voltage reaches 2.9V. An external resistor connected in parallel discharges the capacitor. Switching resumes when the voltage drops to 2V. Synchronization Input. SYNCIN accepts the synchronization signal from SYNCOUT of another MAX5051 and shifts the switching of the synchronized unit by 180 allowing the reduction of input bypass capacitors. The MAX5051 switches at the same frequency at SYNCIN. SYNCIN must be 50% duty cycle. Leave SYNCIN floating if unused.
14
LXL
15 16 17 18
CS DRVL PGND DRVDD
19 20 21
DRVB XFRMRH DRVH
22
BST
23 24 25
AVIN GND UVLO
26
STARTUP
27
FLTINT
28
SYNCIN
10
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
Functional Diagram
9V LDO 5V LDO REG5 OK
MAX5051
PVIN
REG9
REG9 OK 18R OVER TEMP R
REG5
MAX5051
STT THERMAL SHUTDOWN LEVEL SHIFT 25s RISINGEDGE DELAY UVLO 1.25V 1.125V SHDN 60ns RISINGEDGE DELAY
BST DRVH XFRMRH DRVDD DRVL PGND LXVDD
1.25V 1.125V
AVIN
INTERNAL REGULATOR
INTERNAL SUPPLY 1.25V REFERENCE
LEVEL SHIFT 80A
LXH LXL
RCOSC
OSC
SYNCIN SYNCOUT 2.7V/1.8V
FLTINT
RCFF 2.34V CPWM 1 D CON R COMP FB E/A CSS 200ns RISINGEDGE DELAY 64A DRVDD 300ns ONE SHOT 2.7V/1.8V SHDN S Q Q 50A CILIM 156mV 10MHz
CS
STARTUP
SHDN GND
SSA 1.25V
LEVEL SHIFT
DRVB
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
Detailed Description
The MAX5051 controller IC is designed for two-switch forward converter power-supply topologies. It incorporates an advanced set of protection features that makes it uniquely suitable when high reliability and comprehensive fault protection are required, as in power supplies intended for telecommunication equipment. The device operates over a wide 11V to 76V supply range. By using the MAX5051 with a secondary-side synchronous rectifier circuit, a very efficient low output voltage and high output-current power supply can be designed. In a typical application, the AVIN pin is connected directly to the input supply. The PVIN pin is connected to the input supply through a bleed resistor. This is used to charge up a reservoir capacitor. When the voltage across this capacitor reaches approximately 24V, then primary switching commences. If the tertiary winding is able to supply bias to the IC, then self boot-strapping takes place and operation continues normally. If the voltage across the reservoir capacitor connected to PVIN falls below 6.2V, then switching stops and the capacitor starts charging up again until the voltage across it reaches 24V. This device incorporates synchronization circuitry, enabling the direct paralleling of two devices for higher output power and lower input ripple current. Using a single pin, the circuitry synchronizes and shifts the phase of the second device by 180. To enable simultaneous wakeup and shutdown, a STARTUP pin is provided. Connect all the STARTUP pins of all MAX5051 devices together to facilitate parallel operation in the primary side. When each power supply generates different output voltages, connecting the STARTUP pins is not necessary. * Clean modulator ramp and higher amplitude for increased stability; * Stable operating current of the optocoupler LED and phototransistor for maximized control-loop bandwidth (in current-mode applications, the optocoupler bias point is output-load dependent); * Predictable loop dynamics simplifying the design of the control loop. The two-switch power topology has the added benefit of recovering practically all magnetizing as well as the leakage energy stored in the parasitics of the isolation transformer. The lower clamped voltages on the primary power FETs allow for the use of low RDS(ON) devices. Figure 2 shows the schematic diagram of a 48V input 3.3V/10A output power supply built around the MAX5051.
MOSFET Drivers
The MAX5051's integrated high- and low-side MOSFET drivers source and sink up to 2A of peak currents, resulting in very low losses even when switching high gate charge MOSFETs. The high-side gate driver requires its own bypass capacitor connected between BST and XFRMRH. Use high-quality ceramic capacitors close to these two pins for bypass. Under normal operating conditions, the energy stored in the transformer parasitics swings the XFRMRH pin to ground while the transformer is resetting. During this time, the charge on the boost capacitor connected to the BST pin is replenished. However, under certain conditions, such as when the magnetizing inductance of the transformer is very high or when using conventional rectification at the output, the duty cycle with light loads may become very small. Thus, the energy stored could be insufficient to swing XFRMRH to ground and replenish the boost capacitor. Figure 3 shows the equivalent circuit during the magnetizing inductance reset interval, assuming synchronous rectification where the output inductor is not allowed to run discontinuous. If the magnetizing inductance is kept below the following minimum, then the boost capacitor charge will not deplete: LM 0.294 d2 VIN 2 fs Qgtotal + (0.005A) fs
Power Topology
The two-switch forward-converter topology offers outstanding robustness against faults and transformer saturation while allowing the use of SO-8 power MOSFETs with a voltage rating equal to only that of the input supply voltage. Voltage-mode control with feed-forward compensation allows the rejection of input supply disturbances within a single cycle, similar to that of current-mode controlled topologies. This control method offers some significant benefits not possible with current-mode control. These benefits are: * No minimum duty-cycle requirement because of current-signal blanking;
where d is the duty cycle, VIN is the input voltage, fS is the switching frequency, and Qgtotal is the total gate charge for the high-side MOSFET. The above formula is only an approximation; the actual value will depend on other parasitics as well.
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
VIN+ D4 MA111CT R9 15k C11 0.1F R12 1M C8 4.7F R6 47 R5 10 D3 BAT46W
C7 4.7F
STT
CSS
PVIN
AVIN
C12 220nF
SYNCIN
REG9
BST
C5 1F
FLTINT GND RCOSC C13 100pF STARTUP RCFF C14 390pF R13 100k R14 24.9k R15 1M R11 39.2k CON
XFRMRH DRVDD DRVH N3 BSS123
N1 SI4486
T1 LM: 150H P: 14T S: 4T T: 6T
fs = 250kHz
B2100
D1 USED FOR BOOST CAPACITOR PRECHARGE
D5 T1
L1 2H C4 3 x 270F 3.3V 10A RLOAD
MAX5051
DRVB DRVL CS PGND
N2 SI4486 D2 B2100 R4 28m R3 475 U2
UVLO
REG5
LXVDD
COMP
SYNCOUT
LXH
FB
LXL
C3 150nF
R8 2.2k R10 10 C10 4.7F C9 1F C6 270nF R7 360 PS2913 C1 47nF
C2 220nF
R1 11.5k
MAX8515 R2 2.55k
VIN-
Figure 2. Typical Application Circuit
If the charge stored on the boost capacitor is not adequately replenished then the gate-driver lockout for the high-side MOSFET is triggered, stopping the high side from switching. The low side continues switching, eventually recharging the capacitor, at which point the high side starts switching again. To prevent this behavior, use the boost capacitor's cycle-by-cycle charging circuit to prevent unwanted shutdowns of the high side (Figure 2). Connect the gate of a small high-voltage FET (with the same voltage rating or higher as the main FETs) to the DRVB output of the MAX5051. Connect the drain of this FET to XFRMRH, and connect the source to the primary ground. DRVB will briefly (300ns) turn this FET ON every cycle after the main PWM clock terminates. This allows the boost capacitor to be replenished under all conditions, even when switching stops completely. A suitable FET for this is BSS123 or equivalent (100V, 170mA rated). The boost-capacitor charge
IBST
BST IGD
IBST DRVH XFMRH ILM LM
VIN
REG9 DRVL
Figure 3. Boost Capacitor Charging Path During Transformer Reset
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
diode is a high-voltage, small-signal Schottky type. It may be helpful to connect a resistor in series with this diode to minimize noise as well as reduce the peak charging currents. As in any other switching powersupply circuit, the gate-drive loops must be kept to a minimum. Plan PC board layout with the critical current carrying loops of the circuit as a starting point. approximate value of the primary magnetizing inductance of T1: 2.5 RdsLXH + RdsLXL ts LM fs 16 Cds fs
Secondary-Side Synchronization
The MAX5051 has additional (LXH and LXL) outputs to make the driving of secondary-side synchronous rectifiers possible with a signal from the primary. These signals lead in time, the actual gate drive applied to the main power FETs, and allow the secondary-side synchronous FETs to be commutated in advance of the power pulse. The synchronizing pulse is generated approximately 90ns ahead of the main pulse that drives the two power FETs. Synchronization is accomplished by connecting a small pulse transformer between LXH and LXL, along with some clamp diodes (D1 and D2 in Figure 4). This is a small integrated two-switch driver configuration that allows for full recovery of the stored energy in the magnetizing inductance of the pulse transformer, thereby significantly reducing the running bias current of the controller. It also allows for correct transfer of DC levels without requiring series capacitors with large time constants, assuring correct drive levels for the secondary circuit. Select a pulse transformer, T1, so the current buildup in its magnetizing inductance is low enough not to create a significant voltage droop across the internal driver FETs. Use the following formula to calculate the
where RdsLXH and RdsLXL are the internal high- and lowside pulse transformer driver on-resistances, fs is the switching frequency, LM is the pulse transformer primary magnetizing inductance, ts is the transition time at the drains of these FETs (typically < 40ns), and Cds is the total drain-source capacitance (approximately 10pF). Alternatively, a high-speed optocoupler (Figure 5) can be used instead of the pulse transformer. The lookahead pulse accommodates the propagation delays of the high-speed optocoupler as well as the delays through the gate drivers of the secondary-side FETs. Choose optocouplers with propagation delays of less than 50ns.
Error Amplifier And Reference Soft-Start
The error amplifier in the MAX5051 has an uncommitted inverting input (FB) and output (COMP). Use this amplifier when secondary isolation is not required. COMP can then be directly connected to CON (the input of the PWM comparator). The noninverting input of the error amplifier is connected to the soft-start generator and is also available externally at CSS. A capacitor connected to CSS is slewed linearly during initial startup with the 70A internal current source (see Figure 2). This provides a linearly increasing reference to the noninverting input of the error amplifier forcing the output voltage also to slew proportionally. This method of soft-start is superior to other methods because the loop is always
MAX5051
REG5 LXVDD
R1 4.7
MAX5051
REG5 D3 1N4148 R2 2k
R1 4.7 5V R3 560 LXH R2 2k C1 1F PS9715 HIGH-SPEED OPTO C2 U2
D1 LXH
C1 1F T1
LXVDD
LXL D2 PGND T1: PULSE ENGINEERING, PE-68386. D1, D2: CENTRAL SEMICONDUCTOR, CMOSH-3.
LXL
PGND
Figure 4. Secondary-Side Synchronous Rectifier Driver Using Pulse Transformer 14
Figure 5. Secondary-Side Synchronous Rectifier Driver Using High-Speed Optocoupler
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
in control. Thus, the output-voltage slew rate is constant at light or heavy loads. Once the soft-start ends, the voltage on CSS regulates to 1.24V. Do not load CSS with external circuitry. A suitable range of capacitors connected to CSS is from 10nF to 0.1F. Calculate the required soft-start capacitor based on the total outputvoltage startup time as follows: CCSS = 56F / s x t SS where CCSS is the capacitor connected to CSS, tSS is the soft-start time required for the output voltage to rise from 0V to the rated output voltage. This only applies when this amplifier is used for output voltage regulation. and low-side gate drivers. Bypass REG9 with a 4.7F ceramic capacitor or any other high-quality capacitor; use low-value ceramics in parallel as necessary. A 5V regulator also is provided, REG5, primarily used to bias the internal circuitry of the MAX5051. Bypass REG5 with a 4.7F ceramic capacitor similar to the one used for REG9. Both of these regulators are always powered. When using bootstrapped startup through a bleed resistor, do not load these outputs while the MAX5051 is in standby as it may fail to start. Any external loading to this output should be such that the sum of their load and the standby current through PVIN of the MAX5051 is less than the current that the bleed resistor can supply.
MAX5051
Startup Modes
The MAX5051 can be configured for two different startup modes, allowing operation in either bootstrapped or direct power mode. Direct Power Mode In direct power mode, AVIN and PVIN are connected directly to the input supply. This is typical in 12V to 24V systems. The undervoltage lockout set at STT needs to be adjusted down with an external resistor-divider to an appropriate level. Bootstrapped Startup In bootstrap mode, a resistor is connected from the input supply to PVIN, where a capacitor to GND is charged towards the input supply. When this voltage reaches the startup threshold, the device wakes up and begins switching. A tertiary winding from the transformer is then used to sustain operation. The MAX5051 draws little current from PVIN before reaching the threshold, which allows a large-value bootstrap resistor and reduces its power dissipation after startup. A large startup hysteresis helps the design of the bootstrap circuit by providing longer running times during startup. After coming out of standby and before initiating the soft-start, the MAX5051 turns on the low-side FET to charge up the boost capacitor. A voltage detector has been incorporated in the high-side driver that prevents the high-side switch from turning on with insufficient voltage. It is also used to indicate when the boost capacitor has been charged. Once the capacitor is charged, soft-start commences. If the duty cycle is low, the magnetizing energy in the transformer may be insufficient to keep the bootstrap capacitor charged. DRVB (see Figure 2 dotted lines) has been provided to drive a small external FET connected between XFRMRH and PGND, and is pulsed every cycle to keep the capacitor charged.
PWM Ramp
The PWM ramp is generated at RCFF. Connect a capacitor CRCFF from RCFF to ground and a resistor R RCFF from RCFF to AVIN. The ramp generated on RCFF is internally offset by 2.3V and applied to the noninverting input of the PWM comparator. The slope of the ramp is part of the overall loop gain. The dynamic range of RCFF is 0 to 3V, and so the ramp peak must be kept below that. Assuming the maximum duty cycle approaches 50% at minimum input voltage, use the following formula to calculate the minimum value of either the ramp capacitor or resistor: V RRCFF CRCFF INUVLO 2 fs VRPP where VINUVLO is the minimum input supply voltage (typically the PWM UVLO turn-on voltage), f S is the switching frequency, and V RPP is the peak-to-peak ramp voltage, typically 2V. Allow the ramp peak to be as high as possible to maximize the signal-to-noise ratio. The low-frequency smallsignal gain of the power stage, Gps (the gain from the inverting input of the PWM comparator to the output) can be calculated by using the following formula: Gps = Nsp RRCFF CRCFF fs where Nsp is the secondary-to-primary power transformer turns ratio.
Internal Regulators
The MAX5051 has two internal linear regulators that are used to power internal and external control circuits. The 9V regulator, REG9, is primarily used to power the high-
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
Normally PVIN is derived from a tertiary winding of the transformer. However, at startup there is no energy delivered through the transformer, hence, a special bootstrap sequence is required. Figure 6 shows the voltages on PVIN, REG9, and REG5 during startup. Initially, PVIN, REG9, and REG5 are 0V. After the input voltage is applied, C21 (Figure 8) charges PVIN through the startup resistor, R22, to an intermediate voltage. At this point, the internal regulators begin charging C3 and C4. The MAX5051 uses only 400A (typ) of the current supplied by R22, and the remaining current charges C21, C3, and C4. The charging of C4 and C3 stops when their voltages reach approximately 5V and 9V, respectively, while PVIN continues rising until it reaches the wakeup level of 24V. Once PVIN exceeds this wakeup level, switching of the external MOSFETs begins and energy is transferred to the secondary and tertiary outputs. When the voltage on the tertiary output builds to higher than 9V, startup has been accomplished and operation is sustained. However, if REG9 drops below 6.2V (typ) before startup is complete, the device goes back into standby. In this case, increase the value of C21 to store enough energy allowing for voltage buildup at the tertiary winding. Startup Time Considerations The PVIN bypass capacitor, C21, supplies current immediately after wakeup (see Figure 8). The size of C21 and the connection of the tertiary winding determine the number of cycles available for startup. Large values of C21 increase the startup time and supply gate charge for more cycles during initial startup. If the value of C21 is too small, REG9 drops below 6.2V because the MOSFETs did not have enough time to switch and build up sufficient voltage across the tertiary output to power the device. The device goes back into standby and will not attempt to restart until PVIN rises above 24V. Use a low-leakage capacitor for C21, C3, and C4 (see Figure 8). Generally, power supplies keep typical startup times to less than 500ms even in low-line conditions (36VDC for telecom applications). Size the startup resistor, R22 (Figure 8) to supply both the maximum startup bias of the device and the charging current for C21, C3, and C4.
MAX5051
Oscillator and Synchronization
The MAX5051 oscillator is externally programmable through a resistor and capacitor connected to RCOSC. The PWM frequency will be 1/2 the frequency at RCOSC with a 50% duty cycle, and is available at SYNCOUT. The maximum duty cycle is limited to < 50% by a 60ns internal blanking circuit in the power drivers in addition to the gate and driver delays. Use the following formula to calculate the oscillator components: RRCOSC 1 REG5 2 fs (CRCOSC + CPCB ) In REG5 - VTH
PVIN 10V/div
REG9 5V/div
REG5 5V/div 40ms/div
where CPCB is the stray capacitance on the PC board (about 14pF), REG5 = 5V, VTH is the RCOSC peak trip level, and fs is the switching frequency. The MAX5051 contains circuitry that allows it to be synchronized to an external clock whose duty cycle is 50%. For proper synchronization, the frequency of this clock should be 15% to 20% higher than half the RCOSC frequency of the MAX5051's internal oscillator. This is because the external source SYNCIN directly drives the power stage, whereas the internal clock is divided by two. The synchronization feature in the MAX5051 has been designed primarily for two devices connected to the same power source with a short physical distance between the two circuits. Under these circumstances, the SYNCOUT from one of the circuits can be connected to the SYNCIN of the other one; this forces the power cycle of the second unit to be 180 out-of-phase. To synchronize a second MAX5051, feed the SYNCOUT of the first device to the SYNCIN of the second device. If necessary, many devices can be daisy-chained in this manner. Each device will then have 180 phase difference from the device that drives it.
Figure 6. PVIN, REG5, and REG9 During Startup in Bootstrapped Mode
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
Integrating Fault Protection
The integrating fault protection feature allows transient overcurrent conditions to be ignored for a programmable amount of time, giving the power supply time to behave like a current source to the load. This can happen, for example, under load-current transients when the control loop requests maximum current to keep the output voltage from going out of regulation. The fault integration time can be programmed externally by connecting a suitably sized capacitor to the FLTINT pin. Under sustained overcurrent faults, the voltage across this capacitor is allowed to ramp up towards the FLTINT shutdown threshold (2.9V, typ). Once the threshold is reached, the power supply shuts down. A high-value bleed resistor connected in parallel with the FLTINT capacitor allows it to discharge towards the restart threshold (1.8V, typ). Once this threshold is reached, the supply restarts with a new soft-started cycle. Note that cycle-by-cycle current limiting is provided at all times by CS with a threshold of 154mV (typ). The fault integration circuit works by forcing a 90A current out of FLTINT every time that the current-limit comparator (Figure 1, CILIM) is tripped. Use the following formula to calculate the value of the capacitor necessary for the desired shutdown time of this circuit. I t CFLTINT = FLTINT SH 0.9V where IFLTINT = 90A, tSH is the desired fault integration time after the first shutdown cycle during which current-limit events from the current-limit comparator are ignored. For example, a 0.1F capacitor gives a fault integration time of 2.25ms. Some testing may be required to fine-tune the actual value of the capacitor. To calculate the required bleed resistance RFLTINT, use the following formula: RFLTINT = tRT 0.372 x CFLTINT
#1 RCOSC SYNCOUT RCFF CON SYNCIN
MAX5051
MAX5051
FLTINT STARTUP UVLO
#2 RCOSC SYNCOUT RCFF CON SYNCIN
MAX5051
FLTINT STARTUP UVLO
Figure 7. Connection for Synchronized STARTUP of Two or More MAX5051s
helps prevent startup conflicts when the secondaries of the power supplies are paralleled. Connecting SYNCOUT to SYNCIN is not necessary; however, when used, this minimizes the ripple current though the input bypass capacitors.
Applications Information
Isolated Telecom Power Supply
Figure 8 shows a complete design of an isolated synchronously rectified power supply with a 36V to 72V telecom voltage range. This power supply is fully protected and can sustain a continuous short circuit at its output terminals. Figures 9 though 14 show some of the performance aspects of this power-supply design. This circuit is available as a completely built and tested evaluation kit.
where tRT is the desired recovery time. Typically choose tRT = 10 x tSH. Typical values for tSH range from a few hundred microseconds to a few milliseconds.
Synchronizing Primary-Side STARTUP For Parallel Operation
Figure 7 shows the connection diagram of two or more MAX5051s for synchronized primary-side operation. The common connection of STARTUP ensures all paralleled modules wakeup and shutdown in tandem. This
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MAX5051
Parallelable, Clamped Two-Switch Power-Supply Controller IC
Figure 8. Schematic of a 48V Input 3.3V at 15A Output Synchronously Rectified, Isolated Power Supply
XFRMRH +VIN 2 +VIN XFRMRH 1 R29 1 DRVB -VIN 1 4 5V 1 IN U5 EN GND HOLD 5 VOUT VOUT C15 270F 4V C33 1F 10V N.C. 6 WDI 7 2 C16 3.3F OUT REG9 2 2 C32 1F 3 4 21 20 XFRMRH XFRMRH 2 T1 N4 14 3 5V 1 N3 3 2 1 4 C29 0.1F V+ 8 +VIN 8T 5 2 65 1 2T 10 1 87 D7 2 R18 4.7 PVIN R22 15k +VIN C30 5V 0.1F 1 2 3 V+ U7 P_OUT M_OUT IN+ 6 IN- 5 GND 4 6 5 C23 1000pF 2 D5 6 1 4T 4 1 2 C20 220pF R14 150 R17 0.027 1% 3 8 7 N2 C9 1F D3 1 R9 8.2 C34 330pF 1 87 D4 R10 2 3 20 2 C13 270F 4V 56 DRVB REG9 DRVDD PGND 17 4 N_OUT GND U4 2 5 P_OUT ININ+ 6 18 19 R8 8.2 C14 270F 4V R13 47 RESET L1 2.4H 1 D6 D1 2 C8 4.7F R7 0 8 N5 3 C35 1F 5 6 R5 38.3k 1% C10 0.47F 100V C11 0.47F 100V C12 1F 100V C25 0.07F 100V D2 1 3 2 N1 8 7 +VIN 1 RCOSC U1 SYNCIN 28 R4 1M 1% C7 0.22F R6 1M 1%
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MAX5051
FLTINT 2 SYNCOUT RCFF UVLO GND 4 COM 5 CSS AVIN BST DRVH 7 FB DRVB REG5 REG9 PVIN STT LXVDD IC_PADDLE LXH VOUT R20 0 C21 4.7F 80V R19 475 R12 100k 1% VOUT 3 OUT FB TRIM 5 R2 2.55k 1% C36 C28 R1 0.22F 0.047F 11.5k 1% VOUT R23 10 SENSE (+) SENSE (-) U3 C27 0.15F LXL 16 DRVL 15 CS 8 REG9 9 PVIN 10 11 12 XFRMRH 22 23 6 COMP 24 +VIN 25 STARTUP 26 ON/OFF 3 27 REG5 SGND C19 1F 13 14 LXH 5V C31 5V 0.1F 5 4 3 VCC U6 OUT GND CA 2 R28 2k AN 1 R26 560 4 U2 1 3 2 C22 2200pF 2kV REG9 4 IN 1 PGND 2 GND C26 0.1F
REG5
R21 24.9k 1%
C1 100pF
+VIN
R25 100k
TP1
C2 390pF
2
D8
1
C5 4700pF
R16 10.5k 1%
R15 31.6k 1%
C4 4.7F
C3 4.7F
C6 0.1F
REG5
C18 100pF
R27 10
LXH
TP3
REG5
R3 2.2k
C24 1000pF
R11 360
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R24 10 U1: MAX5051 U2: PS2913-1-M U3: MAX8515 U4, U7: MAX5048A U5: MAX5023M U6: PS9715 N1, N2: SI4486 N3, N4: SI4864 N5: BSS123
C17 0.33F
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
95 90 85 EFFICIENCY (%) 80 75 70 65 60 0 2 4 6 8 10 12 14 LOAD CURRENT (A) POWER DISSIPATION (W)
8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 LOAD CURRENT (A)
Figure 9. Efficiency at Nominal Output Voltage vs. Load Current 48V Nominal Input Voltage
Figure 10. Power Dissipation at Nominal Output Voltage vs. Load Current for 48V Input Voltage.
RL = 0.22 VOUT 1V/div VOUT 100mV/div
IOUT 5A/div
IOUT 5A/div
4ms/div
1ms/div 50% > 75% > 50% OF IOUT(MAX), dl/dt = 5A/s
Figure 11. Turn-On Transient at Full Load (Resistive Load)
Figure 12. Output Voltage Response to Step-Change in Load Current
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Parallelable, Clamped Two-Switch Power-Supply Controller IC MAX5051
A VOUT 50mV/div B
IOUT 10A/div
IOUT 10A/div
2s/div
A: 1ms/div B: 20ms/div
Figure 13. Output Voltage Ripple At Nominal Input Voltage and Full Load Current (Scope Bandwidth = 20MHz)
Figure 14. Load Current (10A/div) as a Function of Time When the Converter Attempts to Turn On into a 50m Short Circuit
Pin Configuration
TOP VIEW
RCOSC 1 SYNCOUT 2 RCFF 3 CON 4 CSS 5 COMP 6 FB 7 REG5 8 REG9 9 PVIN 10 STT 11 LXVDD 12 LXH 13 LXL 14 MAX5051 28 SYNCIN 27 FLTINT 26 STARTUP 25 UVLO 24 GND 23 AVIN 22 BST 21 DRVH 20 XFRMRH 19 DRVB 18 DRVDD 17 PGND 16 DRVL 15 CS
Chip Information
TRANSISTOR COUNT: 2049 PROCESS: BiCMOS/DMOS Exposed Paddle Connected to GND
TSSOP
EXPOSED PADDLE IS INTERNALLY CONNECTED TO GND.
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Parallelable, Clamped Two-Switch Power-Supply Controller IC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX5051
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
TSSOP 4.4mm BODY.EPS

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